The present invention relates to integrated circuit packages, and more specifically to an integrated circuit package suitable for high speed processors.
Propagation delays caused by interconnecting wires between logic gates are a major contributing factor in the overall speed of integrated circuitry. Wire delays on LSI chips become increasingly important as circuit density and speed increase. In high speed processors, the wire delay can account for half the overall delay of the system. As circuit density increases there is a corresponding increase in the number of input/output pins according to the known empirical formula P=kG.sup.r, where P represents the pin count, G represents the number of gates, and k and r are constants. If it is desired to mount 5000 gates on a single package, for example, more than 2300 input/output pins would be required. Furthermore, for uniform power distribution the same number of power supply pins would be required.
In a known LSI package as disclosed in U.S. Pat. No. 4,612,601 issued to T. Watari, input/output pins are juxtaposed in alternate relationship with power supply and ground connection pins, requiring a substantial amount of surface area. In addition, for high speed processing, the problems of waveform distortion and crosstalk arise due to mismatched impedances at the input/output pins.